English
First Successful PCIe Gen 3 Controller and PHY Combination on TSMC's 28nm
PLDA and GUC are interviewed by Gabrièle Saucier at DAC 2013
Posted on Monday Jul. 08, 2013
PLDA Channel
Demonstration of a CXL Interconnect on a FPGA-based design
6:03
Learn how to configure a PCIe IP with an AXI interconnect
4:44
Discover how to configure XpressRICH IP
5:09
Test, exercize and debug your PCIe add-in cards with Inspector
3:52
DMA for complex System-on-chip in AI, Automotive and IoT
3:51
DMA for complex System-on-chip in AI, Automotive and IoT
3:51
PCIe Debugging tutorials (Ep1) : 4 common hardware problems
2:24
PCIe solutions for FPGA and ASIC designs
2:11
PLDA Announces PCIe Gen 4 & PCIe Multiport Embedded Switch IP
3:20
PLDA's PCI Express 4.0
1:36
Demonstration of a CXL Interconnect on a FPGA-based design6:03
Learn how to configure a PCIe IP with an AXI interconnect4:44
Discover how to configure XpressRICH IP5:09
Test, exercize and debug your PCIe add-in cards with Inspector3:52
DMA for complex System-on-chip in AI, Automotive and IoT3:51
DMA for complex System-on-chip in AI, Automotive and IoT3:51
PCIe Debugging tutorials (Ep1) : 4 common hardware problems 2:24
PCIe solutions for FPGA and ASIC designs2:11
PLDA Announces PCIe Gen 4 & PCIe Multiport Embedded Switch IP3:20
PLDA's PCI Express 4.0 1:36