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MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5)
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New Verification IP
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WDT Verification IP
- The Watchdog Timer (WDT) regains control in case of system failure to increase application reliability.
- The WDT can generate a reset or an interrupt when the counter reaches a given timeout value.
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GPIO Verification IP
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
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Simulation VIP for AMBA LTI
- LTI active and passive VIP supports both the specification version LTI-A and LTI-B
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Simulation VIP for UCIE
- Support testbench language interfaces for SystemVerilog, UVM
- UVM building blocks
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Universal Chiplet Interconnect Express (UCIe) Verification IP
- Supports Universal Chiplet Interconnect Express Specification Version 1.0, February 2022.
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SPMI Verification IP
- Compliant with MIPI SPMI(1.0 and 2.0) specification.
- Supports multi-master and multi-slave model.
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BoW Verification IP
- Compliant to ODSA Transaction and Link Layer Specification for BoW Interfaces and Bunch of Wires (BoW) PHY specification
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USB4 v2.0 Verification IP
- Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
- Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
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MASS Solution Verification IP
- Support full functionality of APHY as a physical layer
- Support Different PAL for multiple adaption layers for A-pkt conversion
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UCIe Verification IP
- Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
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TCP/TCPSW Verification IP
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
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Simulation VIP for MIPI SoundWire-I3S
- Support testbench language interfaces for SystemVerilog and UVM
- Generates constrained-random bus traffic with predefined error injection
Top Verification IP
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1
Simulation VIP for UCIE
- Support testbench language interfaces for SystemVerilog, UVM
- UVM building blocks
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2
UCIe Verification IP
- Support latest PCIe Gen5/6 and CXL 2.0/3.0
- Device and Retimer supported
- Multiple stacks / multiple protocol
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3
AMBA4 ACE Verification IP
¹ Top Verification IP Over the Last Two Weeks (Last update: Apr. 6)
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