Synopsys VC Verification IP for I2C includes all protocol speeds. With a comprehensive set of protocols, methodology, verification and ease-of-use features, users are able to achieve rapid coverage ...

I2C Verification IP provides an smart way to verify the I2C bi-directional two-wire bus. The SmartDV s I2C Verification IP is fully compliant with version 2.1, 3.0 and 6.0 of the Philip s I2C-Bus ...

I2C-Xactor is a comprehensive memory VIP solution portfolio for I2C and SMBus used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance. I2C-Xactor ...

DDR-Xactor is a comprehensive memory VIP solution portfolio for DDR4/3, LPDDR3/2, RDIMM, LRDIMM (including 3DS), NVDIMM-P/N, DFI-PHY used by SoC and memory controller designers using the external ...

I3C-Xactor is a comprehensive memory VIP solution portfolio for I3C and I2C s used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance. I3C-Xactor ...

The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom ...

The I2C Verification IP provides an effective & efficient way to verify the components interfacing with I2C interface of an ASIC/FPGA or SoC. The I2C VIP is fully compliant with revision ...

eInfochips’ I2C VMM based VIP is highly configurable, reusable, scalable and extensible verification intellectual property that is suitable for verification of I2C Master/ Slave.

UST Global VIP for I2C provides a comprehensive set of verification, methodology and protocol features, thus enabling designers to achieve a faster convergence & closure of I2C designs. I2C ...

The EasyIC synthesizable I3C model is a configurable, fully functional model compliant to the MIPI I3C specification that can be targeted to a range of emulation systems. The synthesizable I3C ...

HMC-Xactor is a comprehensive memory VIP solution portfolio for Hybrid Memory Cube (HMC 2.0) targeting a new standard in memory performance, density, power consumption, and cost. HMC-Xactor ...

DisplayPort VIP is a comprehensive VIP solution for DisplayPort (DP) and eDP source and sink designs. DP VIP implements a complete set of models, protocol checkers, and compliance testsuites ...

Display port is the serial communication protocol developed by Video Electronics Standards Association to support the video,audio and other data between a source device and sink device. Display ...

MIPI I3C Verification IP provides a smart way to verify the MIPI I3C bi-directional two-wire bus. The SmartDV s MIPI I3C Verification IP is fully compliant with MIPI I3C version 1.0, Draft version ...

Display port 2.0 is the serial communication protocol developed by Video Electronics Standards Association(VESA) to support the video,audio and other data between a source device and sink device. ...

HMC Memory Model provides an smart way to verify the HMC component of a SOC or a ASIC. The SmartDV s HMC memory model is fully compliant with standard HMC Specification and provides the following ...

nvSRAM Memory Model provides an smart way to verify the nvSRAM component of a SOC or a ASIC. The SmartDV s nvSRAM memory model is fully compliant with standard nvSRAM Specification and provides ...

SVID Verification IP provides an smart way to verify the SVID bi-directional two-wire bus. The SmartDV s SVID Verification IP is fully compliant with the version 1.2 SVID Specifications and ...

XMBus (Extended Management Bus) Verification IP provides an smart way to verify the XMBus bi-directional two-wire bus. The SmartDV s XMBus Verification IP is fully compliant with version 0.5 ...

IPMB Verification IP provides an smart way to verify the IPMB two-wire bus. The SmartDV s IPMB Verification IP is fully compliant with version 1.0 and provides the following features.

TPM Verification IP enables trust in computing the platforms in general. TPM Verification IP provides an smart way to verify the data transmission between TPM master and slave. The SmartDV s ...

TS5(Thermal Sensor) Verification IP provides an smart way to verify the TS5 bi-directional two-wire bus. The SmartDV s TS5 Verification IP is fully compliant with JEDEC TS5 Specification and ...

The SmartDV Verification IP (VIP) for JESD403 provides an efficient and simple way to verify the JESD403 bidirectional two-wire serial interface. The SmartDV VIP is fully compliant with version ...

The Memory Models for LRDIMM are ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the ...

In production since 2015 on dozens of production design. The Cadence® Verification IP (VIP) for MIPI® I3Csm VIP provides support for the MIPI I3C protocol specification. It provides a mature, ...

Used by market leaders driving the specification. The Cadence® Verification IP (VIP) for DisplayPort is the industry's most comprehensive protocol validation solution for DisplayPort designs. ...

Truechip's DisplayPort version 2.0 Verification IP provides an effective & efficient way to verify the components interfacing with the DisplayPort interface of an ASIC/FPGA or SoC. Truechip's ...

Truechip's MASS Solution VIP provides a complete Verification solution for Mipi Automotive SerDes Solutions (MASS), it is an effective & efficient way to verify the components interfacing with ...

Truechip’s GPIO Verification IP offers a streamlined and efficient solution for verifying GPIO components within an IP or SoC. Truechip's VIP fully adheres to the GPIO Specification version ...