Behavioral DS3 Generator and Analyzer Data Sheet

Features

• Generator Features
• VHDL/Verilog component generates DS3 data. Supports Unchannelized, M23 Multiplex, and DS3 C-bit Parity Applications.
• Supports 5 types of Payload - AIS, Idle, PRBS15, Fixed Pattern, and Data from a File.
• Supports Physical Layer Convergence Protocol (PLCP) over DS3 format.
• Completely configurable via a command language and command interprettor.
• Ability to generate errors on a frame and sub-frame basis on any of the overhead bits.
• Ability to transmit any 16-bit data sequence over the Cbit channel.
• Stuff under command control on a per-frame basis.
• Generate dump and log files.
• Complies with ANSI T1.107-1995.
• Analyzer Features
• Supporting analyzer will monitor DS3 data.
• Built-in framer will frame on DS3 signals or on an external frame sync signal.
• Detects 5 types of Payload - AIS, Idle, PRBS15, Fixed Pattern, and Data from a File.
• Ability to ignore frames to account for data delay through the device.
• Recognizes errors in all overhead bits.
• Completely configurable via a command language and command interprettor.
• Recognizes Stuff bits.
• Generates dump and log files.
• Complies with ANSI T1.107-1995.