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Complete Verification IP Portfolio
Synopsys VC Verification IP (VIP) is architected to address the challenge of verifying today's highly sophisticated and complex SoC designs. The broad portfolio of VC VIP for buses, interfaces and memory is written entirely in SystemVerilog and natively
supports UVM and VMM. VC VIP includes many features to increase verification productivity, reduce time to coverage and increase confidence in protocol compliance. It includes configuration-aware verification plans, built-in functional coverage, error injection, comprehensive error checking and support for Verdi Protocol Analyzer to enable engineers for rapid verification closure. Test suites are available in SystemVerilog UVM source code to accelerate time to achieve compliance verification.
With fast bring-up time, greater performance, protocol-aware debug, a comprehensive verification plan and shorter time-to coverage, VC VIP is ideal for SoC and IP block-level verification.
supports UVM and VMM. VC VIP includes many features to increase verification productivity, reduce time to coverage and increase confidence in protocol compliance. It includes configuration-aware verification plans, built-in functional coverage, error injection, comprehensive error checking and support for Verdi Protocol Analyzer to enable engineers for rapid verification closure. Test suites are available in SystemVerilog UVM source code to accelerate time to achieve compliance verification.
With fast bring-up time, greater performance, protocol-aware debug, a comprehensive verification plan and shorter time-to coverage, VC VIP is ideal for SoC and IP block-level verification.
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