Fully configurable Master, Slave or Monitor IP for verifying any AXI-based interface

Fully configurable Verification IP that emulates activity bus Master or Slave components, or independent compliance Monitors enables the verification of AXI-based devices.
Unique IP generation capability based on Formal Protocol description enables creation of IP that exactly fits the configuration in use, from simple architectures to full support of tagged out-of-order designs.
IP configurable for all protocol features including bus width, data interleaving depth, tag-width etc.

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