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Scalable, On-Die Voltage Regulation for High Current Applications
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IEEE 1149.1 (JTAG) eVC
The JTAG eVC is a scalable and extensible tool built on top of Cadence’s industry leading Specman Elite [TM] platform, bringing best-in-class verification methodologies to test’s universal standard, with excellent reusability and return-on-investment.
From developing a JTAG TAP controller to designing a complete chip-level test architecture, the JTAG eVC can be a valuable tool for identifying design bugs, emphasizing protocol compatibility issues and ensuring smooth interoperability of testability features.
Combine this eVC with the new IEEE 1500 eVC for a complete System-on-Chip DFT verification solution.
From developing a JTAG TAP controller to designing a complete chip-level test architecture, the JTAG eVC can be a valuable tool for identifying design bugs, emphasizing protocol compatibility issues and ensuring smooth interoperability of testability features.
Combine this eVC with the new IEEE 1500 eVC for a complete System-on-Chip DFT verification solution.
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