MHL 2.0 Verification IP

MHL 2.0 VIP provides a simple yet powerful user interface which drastically reduces the time and effort needed to create a verification environment and verify thoroughly to ensure first time right silicon. User can verify the complex design with few test cases in very short time instead of running multiple directed test cases

MHL 2.0 VIP is reusable, highly configurable, pre-verified, plug-and-play verification component developed in SystemVerilog solution for SoC incorporating MHL Ports for Source / Sink / Dongle at Module, Chip and System level.

MHL 2.0 VIP is developed using SystemVerilog, the unified language for Design and Verification.

MHL 2.0 VIP can be used as SINK and SOURCE to verify SOURCE and SINK DUT respectively. MHL 2.0 VIP can also be used as DONGLE. DONGLE behaves very much like SINK

• see the entire MHL 2.0 Verification IP datasheet
• get in contact with MHL 2.0 Verification IP Supplier