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Protocol and Memory aware Debug
With today's complex protocols and memory, debug has become one of the most difficult and time-consuming aspects of functional verification. Verdi Protocol Analyzer, available with the VC Verification IP (VIP) portfolio, is a simulator independent, protocol and memory aware debug environment that enables users to quickly debug with any verification environment and easily share simulation results across teams.
Verdi Protocol Analyzer gives users a graphical view of the transfers, transaction, packets and handshaking of a protocol. It highlights relationships across the hierarchy, visually unraveling the complex behavior of highly interleaved traffic. Verdi Protocol Analyzer enables engineers to quickly understand protocol activity, identify bottlenecks and debug unexpected behavior. Errors, warnings and messages are annotated to rapidly identify problems in the simulation. It is integrated with Synopsys' Verdi and DVE to easily track behavior between protocol views and signal views.
Verdi Protocol Analyzer gives users a graphical view of the transfers, transaction, packets and handshaking of a protocol. It highlights relationships across the hierarchy, visually unraveling the complex behavior of highly interleaved traffic. Verdi Protocol Analyzer enables engineers to quickly understand protocol activity, identify bottlenecks and debug unexpected behavior. Errors, warnings and messages are annotated to rapidly identify problems in the simulation. It is integrated with Synopsys' Verdi and DVE to easily track behavior between protocol views and signal views.
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Block Diagram of the Protocol and Memory aware Debug Verification IP
