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ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
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SGPIO Verification IP
SGPIO (Serial GPIO) Bus Verification IP provides an smart way to verify the SGPIO bus. The SmartDV's SGPIO Verification IP is fully compliant with SFF-8485 Specification Revision 0.7 Specification and provides the following features.
SGPIO Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SGPIO Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
SGPIO Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SGPIO Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
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Block Diagram of the SGPIO Verification IP Verification IP
