Simulation VIP for DDR5

In production since 2014 on dozens of production designs.

This Cadence^® Verification IP (VIP) supports the JEDEC^® Memory Device DDR5 SDRAM standard. It provides a highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for DDR5 SDRAM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

The DDR5 standard is the next generation of DRAM device memory standard with many improvements in performance, reliability, and power saving over the previous generation of DRAM devices, DDR4. DDR5 addresses industry demand with increased bandwidth, capacity, power-saving features, and with more reliability through CRC and ECC.

Supported specification: JEDEC JESD79-5 specification.

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