Simulation VIP for eUSB

The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.

Product Highlights
- Includes OTG support
- Optional SuperSpeed Inter-Chip (SSIC) simulation VIP
- Optional PureSuite product with extensive pre-silicon compliance tests

• see the entire Simulation VIP for eUSB datasheet
• get in contact with Simulation VIP for eUSB Supplier