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Simulation VIP for HyperFlash
Hyperflash in production since 2018 for many production designs.
The Cadence® Memory Model Verification IP (VIP) for HyperFlash provides verification of HyperFlash Controller using the HyperBus protocol. It provides a mature, highly capable compliance verification solution applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for HyperFlash is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
Supported specification: Features of Cypress specification Document Number: 001-99198 Rev. *H Revised February 06, 2017.
The Cadence® Memory Model Verification IP (VIP) for HyperFlash provides verification of HyperFlash Controller using the HyperBus protocol. It provides a mature, highly capable compliance verification solution applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for HyperFlash is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
Supported specification: Features of Cypress specification Document Number: 001-99198 Rev. *H Revised February 06, 2017.
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Block Diagram of the Simulation VIP for HyperFlash Verification IP
