Simulation VIP for MIPI DSI-2

In production since 2008 on dozens of production designs.

Cadence provides a mature and comprehensive Verification IP (VIP) for the DSI-2sm protocol, which is part of the MIPI^® family. Incorporating the latest protocol updates, the mature and comprehensive Cadence^® Verification IP for DSI-2sm Protocols provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for DSI-2 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: MIPI for DSI v1.3.1,  DSI2 v1.0, v1.1, DSI2 v2.0 and DPHY v1.2, v2.0, v2.1 and CPHY v1.1, and v1.

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