Simulation VIP for SPI

This Cadence^® Verification IP (VIP) provides support for the SPI protocol. The SPI VIP provides a complete bus functional model (BFM) and integrated automatic protocol checks. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the Cadence SPI VIP helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Cadence VIPs run on all major simulators and supports the SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specifications: Samsung SPI based on the Exynos 5250 spec Revision 1.00, Motorola SPI based on Block Guide V03.06 and SafeSPI SPI for Automotive Safety V0.15.

• see the entire Simulation VIP for SPI datasheet
• get in contact with Simulation VIP for SPI Supplier