Simulation VIP for TileLink

This Cadence^® Verification IP (VIP) provides support for the TileLink specification. It provides a highly capable compliance verification solution simulation, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for TileLink runs on all leading simulators. It supports user interfaces in SV-UVM, plain SV, and C. The VIP includes a bus functional model (BFM) with automatic protocol checkers, supports random stimuli, and collects functional coverage. Cadence provides an integrated solution for interconnect verification that supports the verification of coherent interconnect and performance analysis that provides automated generation of testbenches. The VIP provides a framework for system-level coherency, integrated automatic protocol checks and coverage model.

The TileLink protocol is a standard of the RISC-V Foundation^® designed for RISC-V processors. TileLink is a chip-scale interconnect standard providing multiple managers with coherent memory-mapped access to memory and other subordinate devices. TileLink is designed for use in a SoC to connect general-purpose multiprocessors, co-processors, accelerators, DMA engines, and simple or complex devices, using a fast-scalable interconnect providing both low-latency and high-throughput transfers.

Supported specification: TileLink specification versions 1.7.1 and 1.8.

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