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Source Code Test Suites USB4, 3.2, 3.1, 3.0, 2.0
Synopsys® VC Verification IP for USB provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of USB Hosts, Devices and Hubs with support for Super Speed, High speed, and Full Speed, Extended Super Speed, and Low Speed modes.
VC VIP is based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the need for language translation wrappers that affects performance and ease-of-use. VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.
VC VIP is based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the need for language translation wrappers that affects performance and ease-of-use. VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.
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Block Diagram of the Source Code Test Suites USB4, 3.2, 3.1, 3.0, 2.0 Verification IP
