Synopsys Verification IP for LPDDR4

Synopsys® VC Verification IP for the JEDEC LPDDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on LPDDR4 based designs. VC VIP LPDDR4 is integrated with Verdi Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand view of memory operations along with a consolidated view of the entire memory address space. VC VIP LPDDR4 is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests. In addition to providing LPDDR protocol verification, the Synopsys LPDDR4 VIP can be dynamically configured to model any memory vendor component.

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