VC Verification IP for DDR5

Synopsys® VC Verification IP for JEDEC DDR5, deployed in November 2016, provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of DDR5/4/3/2 based designs.

This VIP is based on next generation architecture and implemented in native SystemVerilog/UVM. It is natively integrated with Verdi Protocol and Memory Analyzer for easy and fast debug and Verdi Performance Analyzer to find and fix performance bottlenecks.

• see the entire VC Verification IP for DDR5 datasheet
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