VC Verification IP for UFS

Synopsys® VC Verification IP for the JEDEC UFS memory protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on UFS based designs. VC VIP for UFS is integrated with Verdi Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand view of protocol traffic. VC VIP for UFS is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests. VC VIP for UFS includes support for MIPI Alliance UniPro and M-PHY protocols.

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