Verification IP for DDR3 (UDIMM, RDIMM, LDIMM)

Synopsys® VC VerificationIP for the JEDEC DDR3 memory protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on DDR3 based designs. VC VIP DDR3 is integrated with VC Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, view of memory operations along with a consolidated view of entire address space of Memory. VC VIP DDR3 is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests.

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