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Verification IP I2C
UST Global VIP for I2C provides a comprehensive set of verification, methodology and protocol features, thus enabling designers to achieve a faster convergence & closure of I2C designs.
I2C VIP is implemented in System Verilog and UVM and is capable of running on all standard simulators. The VIP can be configured, integrated with minimal effort, at the same time, providing a lot of customization.
I2C VIP is implemented in System Verilog and UVM and is capable of running on all standard simulators. The VIP can be configured, integrated with minimal effort, at the same time, providing a lot of customization.
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Block Diagram of the Verification IP I2C Verification IP
