Verification IP UART

UST Global VIP for UART provides a comprehensive set of verification, methodology and protocol features, thus enabling designers to achieve a faster convergence & closure of UART designs. UART VIP is implemented in System Verilog and UVM and is capable of running on all standard simulators. The VIP can be configured, integrated with minimal effort, at the same time, providing a lot of customization.

• see the entire Verification IP UART datasheet
• get in contact with Verification IP UART Supplier