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PCIe - PCI Express Controller

• Fully synthesizable Register Transfer Level (RTL) Verilog HDL core
• Test Bench. (Environment Variable : Verilog)
• Methodologies - based Test Bench : UVM

Securyzrâ„¢ neo Core Platform - One core, multiple products

• Secure Boot
• Firmware update in the field
• Secure key storage

DDR5 Registering Clock Driver (RCD) (DDR5RCD03)

• Compliance as per JEDEC's JESD82-513
• In I3C mode, SCL Operating speed 12.5MHz as Maximum
• DDR5 server speeds up to 6000MT/s

InCore Azurite Series: 32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.

• 32-bit RISC-V core
• 2-stage pipeline
• Available in many versions

DisplayPort 1.2a TX PHY targeting 28nm Artix-7

14-stereo AAC-LC Audio Encoder

• All encoders use the Fraunhofer IIS software
• Configurable output latency useful to synchronize with other sources (up to 8 frames)

Pulse Per Second (PPS) Clock to PPS core

DisplayPort 1.4 IP-core

• Compact RTL footprint
• Easy-to-use
• Simple API

VPU R3.0 on Artix 7 100T

VPU R1.0 on Artix 7 200T

VPU R2.6 on Artix 7 200T

VPU R3.0 on Artix 7 200T