| Today's intellectual-property ecosystem comprises several components and transactions, which have numerous interdependencies and challenges. Key players include IP developers, integrators, semiconductor foundries and, especially now, industry bodies. The goal is to provide a smooth, efficient system for IP to be scoped, developed, transferred, integrated and built within this ecosystem. To grow profitable businesses, the stakeholder companies must be able to estimate what costs and obstacles they face in passing IP through the IP ecosystem and to work with industry bodies to minimize them. This article will describe the IP ecosystem and discuss some aspects with respect to hard IP (mixed signal, RF, digital, for example). It will outline some of the challenges companies face today and methods being taken to advance this topic. When we think about an IP ecosystem, the first observation is that there is a lack of clarity and organization about what this really is. What are the main objects in this ecosystem and how do they interact? Which transaction points between the different stakeholders/players are costly and ineffective today? A good place to start would be where to go to find answers in a material and coordinated fashion. Next, think about what is apparent in the ecosystem, from the fragmented knowledge understood today, focusing on one or two critical transaction points. Standards, industry bodies
Many industry and standards bodies focus on specific engagements and strategic focus items relevant to founding companies. This has led to effective point-to-point engagements. The Spirit interface standard, for example, is being developed around the needs of the founding members. Although effective, due to the direct nature of the engagement, these point-to-point projects do not help IP vendors and integrators understand where to go next or how to solve one problem in the context of the overall cost and inefficiency of the ecosystem. The Virtual Socket Interface Alliance is an umbrella organization working with other industry organizations to ensure that all views are represented. This works well, for example, in VSIA's engagement with the Fabless Semiconductor Association (FSA), which is working on the hard-IP portion of the VSIA Quality IP Metric. The FSA has a broad membership base and represents the important and unique view of fabless companies and key foundries. The VSIA, technically deep and nonaligned, focuses on developing standards for interfaces between different points in the ecosystem. These groups complement each other and expand the resources toward solving key IP challenges while ensuring that many different views are represented. The ecosystem today
What does this ecosystem look like? The figure below shows a holistic view, indicating key phases of IP development and movement. Interestingly, the foundries (in tan) play a role in this and their issues and interchanges with the IP vendors (red) and IP integrators (yellow) must be integrated into this ecosystem. Without the foundries in the picture, this ecosystem is difficult to understand, model and predict — especially given the dependencies that the IP has on the technology (dotted lines). For example, the vendor's IP design depends heavily on the process technology definition and availability. Similarly, the foundry qualification of the vendor's IP depends on its being available for tapeout on a test site. Finally, the integrator's ability to choose and evaluate IP (often) depends on the selection of IP available and qualified by the foundry. In the case of integrated device manufacturers (IDMs), this ecosystem is subtler, since many of the interfaces can be informal and difficult to measure. Nevertheless, the described steps are still valid and a model would apply to both pure-plays and IDMs. Specific projects address some of the issues in the ecosystem. I lead one of these efforts, nurturing the development of a "Quality IP Metric" for hard IP — digital, analog/RF, mixed signal — and mixed hard-soft IP. The Quality IP Metric work is led by Kathy Werner, reuse manager at Freescale Semiconductor Inc. and chairperson of the VSIA IP Quality Pillar. The "hard" portion of the QIP Metric is co-sponsored by VSIA and FSA, with team members from more than a dozen companies. It was critical to have the FSA's views represented. The group goal is to produce a hierarchical questionnaire addressing key detailed technical issues in the handoff of hard IP. This involves producing comprehensive and detailed documentation, covering all aspects of IP design/ packaging, technical focus areas (such as design for manufacturability) and the many different design types (e.g., data converters, I/Os). Just as important is the usability of the document, which poses challenges on reducing the master list of issues, as well as the role of any numeric metric when using the document. This activity has already gone through some key phases. The hard-IP Metric is expected to roll out to the industry in the first part of next year. 1. Build a balanced document. Assign an owner for each section, then draft the needed questions. 2. Cover focus areas. Remix assignments, so that there is an owner for each focus area. Add new questions. 3. Cover design types. Remix assignments, so that there is an owner for each design type. Add new questions. 4. Reduce document. Agree on the maximum document size and questions per section as a team; assign an owner for each section and reduce the sheet to key questions only. 5. Remove duplication. Discuss each duplicated question. 6. Move to beta testing cycle. Raminderpal Singh is director of the Virtual Socket Interface Alliance (VSIA).  See related image | 
