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Innosilicon Technology Ltd
UALink PHY + Controller
Truechip Solutions
MIPI PAL Verification IP
Global IP Core Sales
Zigbee Transceiver PHY IP Core
MEMTECH
LPDDR4x/LPDDR4/DDR4 Memory Controller with high bandwidth and performance
Digital Blocks, Inc.
SPI MRAM/PSRAM Memory Controller

Blogs

Audio AI at the Edge: When the Tiniest Devices Learn to Listen
Ceva, Inc.
Tomer Badug
Ceva, Inc.
Falcon without floating-point
PQShield
PQShield
The silent cryptographic revolution: upgrading the Internet’s security
PQShield
Matthew Stubbs
PQShield
Advanced Packaging Changes the Rules for Semiconductor Health and Performance Management
proteanTecs
proteanTecs
Securing the future of European connected devices: the Cyber Resilience Act (CRA)
PQShield
Matthew Stubbs
PQShield
Memory-Aware ASIC Design for AI Workloads
MosChip Technologies, USA
Siva Raghu Ram Voleti
MosChip Technologies, USA
Simple Mode, Advanced Mode: A Clear Path to Closing Timing Around eFPGA
QuickLogic Corp.
Mao Wang
QuickLogic Corp.
PQShield attends PQC migration workshop
PQShield
Matthew Stubbs
PQShield
PQCryptoLib-Core v3.5.1 Achieves NIST CAVP Certification
PQShield
PQShield
IDS-NoC: A Scalable Interconnect Solution for Modern SoC Design
Agnisys, Inc.
Mohit Saxena
Agnisys, Inc.
Beyond the Fab: Building Europe’s Next Generation of Semiconductor Champions
EnSilica
Ian Lankshear
EnSilica
Defining Automotive Functional Safety through Hardware to AI
MosChip Technologies, USA
Rohita Gupta
MosChip Technologies, USA

Articles

Detect, Diagnose, and Debug using Sensors and Functional Monitoring
Siemens EDA
Siemens EDA and Movellus
Siemens EDA
Practical AI Silicon on Mainstream Node using LPDDR
OPENEDGES Technology, Inc.
OPENEDGES Technology, Inc.
From Specification to Silicon: Using PUFrt to Address Caliptra Root of Trust Integration Challenges
eMemory Technology Inc.
eMemory Technology Inc.
Cache Coherency 101: Why It Matters in Multi-Core SoCs
Signature IP Corporation
Signature IP Corporation
Why SoC Interconnects Have Outgrown the Bus
Signature IP Corporation
SignatureIP Engineering Team
Signature IP Corporation
High-Speed SerDes Design: Architecture, Equalization, and CDR Circuits
MosChip Technologies, USA
Vivek Babu Avuri
MosChip Technologies, USA
Architecting the Future: Building Smarter SoCs with RISC-V
Aion Silicon
Paul Martin
Aion Silicon
AI-Accelerated Software Security Vulnerability Discovery: Is Hardware Next?
Arteris
Andreas Kuehlmann, General Manager – Security Solutions
Arteris
7 Ways to Efficiently Scale IP Lifecycle Management
IC Manage
IC Manage
Case Study: Completing CDC sign-off by linking static & dynamic verification – with Real Intent Meridian CDC
Real Intent
Real Intent
Beyond the Firewall: Hardware-Enforced Network Isolation for Critical OT Infrastructure
CetraC
CetraC
Detect, Diagnose, and Debug using Sensors and Functional Monitoring
Siemens EDA
Movellus & Siemens EDA
Siemens EDA
Asic Technology
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