Design & Reuse
Partner Highlight

New Products

Mobiveil Inc.
Gen6-AglxTM
Dolphin Semiconductor
Ultra low-power crystal-based 32 kHz oscillator in TSMC 12FFC
TES Electronic Solutions
8MHz / 40MHz Pierce Oscillator
Alphacore, Inc.
5 GHz 150 fs jitter Phase Locked Loop (PLL) IP Block GlobalFoundries 22nm
Agnisys, Inc.
Network on Chip (NoC)

Blogs

ISE 2026 Recap: IntoPIX Showcases IPMX, JPEG XS, 8K And AI-Powered Workflows
intoPIX
intoPIX
ChiPy®: Bridge Neural Networks and C++ on Silicon — Full Inference Pipelines with Zero CPU Round-Trips
Quadric
Quadric
Chiplet innovation isn’t waiting for perfect standards
Arteris
Andy Nightingale
Arteris
Powering the AI Supercycle: Design for AI and AI for Design
Cadence Design Systems, Inc.
Reela Samuel
Cadence Design Systems, Inc.
Advancing High‑Performance Silicon Photonics and Silicon Germanium (SiGe) for the Next Era of Optical Connectivity
Radhika Arora
GlobalFoundries
Synopsys Delivers First Complete UFS 5.0 and M‑PHY v6.0 IP Solution for Next‑Gen Storage
Synopsys, Inc.
LJ Chen
Synopsys, Inc.
Flexible Ethernet IP Licensing for Secure, Scalable Silicon Development
Comcores
Comcores
Transforming the Automotive Experience with Cadence Tensilica DSPs
Cadence Design Systems, Inc.
SriramK
Cadence Design Systems, Inc.
Accelerating Multi-Die Innovation: How Synopsys and Samsung are Shaping Chip Design
Synopsys, Inc.
Amlendu Shekhar Choubey
Synopsys, Inc.
Accelerating Chiplet Innovation with a New Partner Ecosystem
Cadence Design Systems, Inc.
Mick Posner
Cadence Design Systems, Inc.
From Fab to the Field: Accelerating Trusted U.S. Semiconductor Onshoring for Mission-Critical Defense
GlobalFoundries
IC Manufacturing and Packaging: The Engine Powering the Digital and AI World
Maven Silicon
P R Sivakumar
Maven Silicon

Articles

Beyond the Core: Tackling system-wide debugging for complex SoCs with Tessent UltraSight
Francisca Tan, Senior Product Manager, Tessent Embedded Analytics
Siemens Digital Industries Software
Securing UALink: Introducing Synopsys UALinkSec_200 Security Module
Synopsys, Inc.
Dana Neustadter, Vincent van der Leest
Synopsys, Inc.
Creating a Frequency Plan for a System using a PLL
Perceptia Devices
Julian Jenkins
Perceptia Devices
PUF-PQC Integrated with PUFrt to Solve PPA Challenge for SoCs
eMemory Technology Inc.
eMemory & PUFsecurity
eMemory Technology Inc.
From Silos to Systems, from Data to Insight
Keysight Technologies
Keysight Technologies
Security certification and the crucial role of anti-tamper sensor solutions
Agile Analog
Chris Morrison
Agile Analog
Beyond the Core: Tackling system-wide debugging for complex SoCs with Tessent UltraSight
Siemens EDA
Francisca Tan, Senior Product Manager
Siemens EDA
Three Ethernet Design Challenges in Industrial Automation
Key ASIC
Key ASIC
ST silicon photonics and BiCMOS technologies: the winning portfolio for AI optical interconnects
STMicroelectronics
STMicroelectronics
AI in VLSI Physical Design: Opportunities and Challenges
Japesh Kumar, Qualcomm
AI-Driven and Traditional Approaches to Accident Scenario Reconstruction
Vayavya Labs
Nitin Swamy
Vayavya Labs
From Theory to the Field: Why Side-Channel Protection Defines Post-Quantum Security
PQSecure Technologies
PQSecure Technologies
Asic Technology
Select your target foundry and technology
FPGA and eFPGA Corner
Select your target vendor and device
Today on Design And Reuse

bullet_arrow  Arteris Network-on-Chip IP Deployed in Renesas’ Next-Gen R-Car Automotive Technology - March 24, 2026

bullet_arrow  CAST Introduces PDM-to-PCM IP Core for Easy Interfacing of Digital Microphones with SoCs - March 24, 2026

bullet_arrow  TDE000S – Secure, Compact RISC-V IP Core Processing - March 24, 2026

bullet_arrow  Jmem Tek Joins GlobalFoundries Ecosystem to Expand Post-Quantum Security Solutions - March 23, 2026

bullet_arrow  Synopsys' vision for engineering the future - March 23, 2026

bullet_arrow  India Making Significant Progress Toward Semiconductor Workforce Development Under C2S - March 23, 2026

Partner Highlight
Latest News Alerts