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New Products

Falcomm
FGN1722: A 2.5W/4W 17-22 GHz High-efficiency GaN Power Amplifier
Mixel, Inc.
MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP in TSMC 16FFC
IP Cores, Inc.
Ultralow-Latency Single-Engine Decompressor Core
Truechip Solutions
UAL Verification IP
ElectraIC
Poly IP Core

Blogs

The security imperative for software-defined vehicles
Rambus, Inc.
Paul Karazuba
Rambus, Inc.
Why analog anti-tamper security IP is crucial in the PQC era
Agile Analog
Chris Morrison
Agile Analog
Why 28nm is the New Strategic Node?
MosChip Technologies, USA
Karthik Kannan
MosChip Technologies, USA
How JPEG XS powered all 104 FIFA® World Cup matches
intoPIX
Julie Van Roy
intoPIX
ETSI Raises the Bar for Secure Boot Under the Cyber Resilience Act
Crypto Quantique
Chris Jones
Crypto Quantique
Why AI's Next Growth Phase Is Redefining Data Center Infrastructure
Renesas
Zaher Baidas
Renesas
Embedded Security explained: Secure boot for embedded systems
KiviCore
KiviCore
Building Privacy-First AI on Android with Local LLM Inference
MosChip Technologies, USA
Prajapati Meet
MosChip Technologies, USA
What are DDR5 DIMM Chipsets? The Complete Guide to RCDs, PMICs, SPD Hubs and More
Rambus, Inc.
Rambus, Inc.
Australia issues guidance on evaluating third-party quantum readiness
PQShield
Matthew Stubbs
PQShield
Understanding security certification and how analog IP can help
Agile Analog
Chris Morrison
Agile Analog
AI Infrastructure Starts Beyond the Chip
Cadence Design Systems, Inc.
Cadence Design Systems, Inc.

Articles

Cache Coherency 101: Why It Matters in Multi-Core SoCs
Signature IP Corporation
Signature IP Corporation
Why SoC Interconnects Have Outgrown the Bus
Signature IP Corporation
SignatureIP Engineering Team
Signature IP Corporation
High-Speed SerDes Design: Architecture, Equalization, and CDR Circuits
MosChip Technologies, USA
Vivek Babu Avuri
MosChip Technologies, USA
Architecting the Future: Building Smarter SoCs with RISC-V
Aion Silicon
Paul Martin
Aion Silicon
AI-Accelerated Software Security Vulnerability Discovery: Is Hardware Next?
Arteris
Andreas Kuehlmann, General Manager – Security Solutions
Arteris
7 Ways to Efficiently Scale IP Lifecycle Management
IC Manage
IC Manage
Case Study: Completing CDC sign-off by linking static & dynamic verification – with Real Intent Meridian CDC
Real Intent
Real Intent
Beyond the Firewall: Hardware-Enforced Network Isolation for Critical OT Infrastructure
CetraC
CetraC
Detect, Diagnose, and Debug using Sensors and Functional Monitoring
Siemens EDA
Movellus & Siemens EDA
Siemens EDA
SOS Core: Reliable, High Performance Design Data Management for Semiconductor Engineering Teams
Keysight Technologies
Keysight Technologies
Case Study: Multipolicy SoC Linting Methodology with Real Intent Ascent Lint
Real Intent
Real Intent
Accelerate Your Innovation: Why FPGA System on Modules (SoMs) Are the Strategic Choice
ElectraIC
ElectraIC
Asic Technology
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FPGA and eFPGA Corner
Select your target vendor and device
Today on Design And Reuse

bullet_arrow  Arm Holdings plc reports results for the first quarter of the fiscal year ending 2027 - August 3, 2026

bullet_arrow  SEMI reports 7.4% rise in silicon wafer shipments - August 3, 2026

bullet_arrow  Marvell commits $250m to India expansion as AI and semiconductor development accelerates - August 3, 2026

bullet_arrow  Cyber Resilience Act, Part 2: Security by Design becomes mandatory - August 3, 2026

bullet_arrow  Engineering Matter-ready Home Automation Solutions with Reusable Blueprints - August 3, 2026

bullet_arrow  Radiation-Hardened by Design: Building Interfaces for Space and Nuclear on TSMC CMOS - August 3, 2026

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