Ensuring Serial Protocol Signal Integrity with FPGAs and Embedded Transceivers

By Bob Blake, Altera Corporation

Today’s high-end field programmable gate arrays (FPGAs) with embedded transceivers support a variety of widely accepted serial protocol standards, including Gigabit Ethernet, PCI Express, XAUI and Serial Rapid IO. Maintaining signal integrity is a key element for the successful implementation of these standards within high bandwidth applications. This can be particularly difficult, however, because of the peculiar characteristics of printed circuit boards (PCBs) which will deteriorate signal quality. FPGAs with built-in transceivers provide adjustable dynamic pre-emphasis, equalization and output voltage controls to help overcome signal deterioration on PCBs, delivering excellent signal integrity.

Unfortunately, ensuring signal integrity is about to become even more challenging as design requirements and second generation protocols lift data transfer rates higher. In essence, transceivers will have to operate between 155Mbps and 12. Gbps to support current applications. In reviewing today’s transceiver marketplace, some adjustments will be needed in transceiver design to ensure signal integrity via effective jitter performance, while maintaining a robust low power and economically viable solution.

Overcoming Board Losses

Transceivers have become commonplace in many applications across all markets, from broadcast, test and measurement, and storage, to the more established wireless and networking applications. This drive, fueled by the desire to move more data, is supplemented by the emergence of many new transmission protocols.

Despite widespread acceptance, however, transceivers bring some complexity of their own. Obviously all board interconnects are transmission lines, but at lower data rates transmission line effects have little influence on signal integrity or the ability for the signal to correctly transmit and receive. However, as the speed increases or, more importantly, as the signal edge rates increase, transmission line characteristics become more relevant. Poor termination, badly placed traces or discontinuities in connector or board vias will deteriorate the signal. Many of these issues can be overcome by using on-chip termination, careful board layout and good quality connectors, although as data rates rise, these issues require more and more design effort.

One key area which cannot be controlled purely by board layout is high frequency signal attenuation or losses caused by the PCB itself. The high frequency losses cause data dependant jitter (DDJ), also known as inter-symbol interference, which prevents the signal from reaching its full strength within its symbol time, causing it to spread into the next signal. This high frequency attenuation is created by two key functions, skin effect and dielectric loss.

Transceivers tend to include additional circuitry in the buffer to overcome high frequency attenuation. This circuitry modifies the signal to allow the data to be interpreted correctly. At the transmitter, pre-emphasis (also known as de-emphasis by some protocols standards bodies) is used to help overcome the problem. Pre-emphasis boosts the strength of the first symbol sent after a transition in the data level (either 1 to 0 or 0 to 1), basically adding high frequency components back into the waveform.

Figures 1a and 1b show the effect of a 6.375-Gbps signal traveling along a 34-in. (860-mm) PCB trace. The top diagram of figure 1a shows the eye as it leaves the transmitter; the bottom diagram shows the eye as it arrives at the receiver. Figure 1b shows the same setup, this time the signal includes 9.5db of pre-emphasis, which appears as overshoot and undershoot in the top diagram. The receiver eye diagram shown at the bottom is now more open.



Figure 1a. Effects of transceiver without pre-emphasis
   

Figure 1b. Effects of transceiver with 9.5 db of pre-emphasis.


Pre-emphasis can help overcome high frequency attenuation, but does come with some side effects due to the boosted signal:

• Increased power requirement
• Increased crosstalk in the system
• Increased EMI in the system

A complementary solution, known as equalization, can also be provided within the receiver. During equalization, a signal entering a receiver will first pass through a high pass filter, which will allow the high frequency signal components through, but attenuate the low frequency components so the signal is reassembled; it also has the benefit of removing low frequency noise. The signal then passes through a buffer stage in which the signal can be brought back to the original level. The signal can then pass into the receiver buffer. Figure 2 shows a simulation of a signal before and after equalization.


Figure 2a. Simulation of signal prior to receiver equalization.


Figure 2b. Simulation of signal post receiver equalization.


Altera’s Stratix GX transceiver FPGA provides multiple levels of pre-emphasis and equalization, which are dynamically controllable. PCB layouts vary, so in many cases it is necessary to simulate the layout to calculate the exact levels. Accurate SPICE models of the transceivers and specific design kits for popular PCB simulation tools are made available to help with this process. However, dynamic control of these features ensures engineers can change levels during configuration or system operation if adjustments are necessary. This functionality enables Stratix GX to operate at 3.125Gbps on FR4 PCB lengths in excess of 1M.

As data rates increase, the need for functionality in the transceiver becomes more important. Stratix II GX, for example, will operate at up to 6.375Gbp, again across transmission line lengths of 1M. These data rates are achieved by providing additional levels of pre-emphasis and equalization; Stratix II GX can offer up to 500% pre-emphasis and up to 19db of equalization. Pre-emphasis and equalizer circuitry has also been modified to make the filters more responsive to higher frequency signals. These enhancements enable the transceivers to successfully operate at the highest data rates across standard FR4 PCB fabric.

Managing Jitter in the PLL

Managing jitter is a significant factor in maintaining signal integrity. It is important that the transceiver manufacturer provide a device with excellent jitter parameters because the operational environment will exaggerate any weaknesses in the transceiver. Manufacturers need to make some difficult decisions when developing next generation architecture. The combination of legacy and new serial protocols operate in a wide range of data rates between 155Mbps and 11.1Mbps. Designing a transceiver to operate across the whole data range requires significant compromise in order to manage jitter performance.

A PLL operating across a wide data range will need multiple bands or virtual PLLs to provide adequate jitter response. This type of circuitry would certainly add complexity to the transceiver although, more importantly, it also would add silicon die area and boost power. Additionally, jitter performance at one data rate does not correlate to jitter performance at a higher or lower data rate because PLL banding component response would differ with data rate. In other words, good performance at one data rate would not guarantee performance at another.

An alternative compromise is to analyze the customer requirement and select a narrower band of operation. Figure 3 provides a chart of protocols by data rate. Today most protocols operate between 1Gbps and 3Gbps.


Figure 3. Protocol by data rate. Stratix II GX will be able to support the protocol sweet spot air directly; lower data rates can be supported by over-sampling the data.


Transceivers within Stratix II GX have been designed to target the “sweet spot” of the current generation of designs. By selecting a data rate between 622Mbps and 6.375Gbps it is possible to develop a PLL architecture capable of delivering excellent jitter performance, while using and maintaining the minimum die area, and at the same time reducing transceiver cost and power requirements. Altera has selected a dual PLL architecture within the transceiver quad. PLL1 will operate between 622Mbps and 3.2Gbps, while PLL 2 will operate between 2.5Gbps and 6.37 Gbps. Each of the four transceivers in the quad will have access to both PLLs so they can run at different data rates. Again, the PLLs are dynamically controllable, allowing the user to change the transceiver data rate while the other transceivers continue to run.
Conclusion

The explosion in transceiver usage is set to continue and expand into different applications, with many protocols set to provide new revisions with even higher data rates. FPGAs with integrated transceivers provide the ideal solution to support the applications and protocols, providing a complete solution from development to characterization and simplifying the customer design cycle. Transceivers do bring some additional complexity to PCB design and board layout, so it is the responsibility of the transceiver manufacturer to supply a product with features that maintain signal integrity by providing excellent jitter performance.