Automated tool suite speeds SoC design

Ralph von Vignau, Philips Semiconductors
(12/12/2005 9:00 AM EST)
EE Times

You can spend a month hand-crafting the last few hundred square microns of silicon out of a SoC (System-on-Chip) design, or you can put your product on the market one month quicker.

Forget the hand-crafting! In today’s fast-moving consumer electronics industry, achieving short time-to-market is the single most effective way of maximizing semiconductor sales and profit. The chances are you will still be able to push the SoC down the price curve by migrating it to a next-generation CMOS process technology within 18 months or so.

In addition to providing cost-down on existing designs, each new CMOS process is going to allow the design of ever more complex chips. Reducing time-to-market for these new designs will therefore require you to manage an ever-increasing level of complexity in a way that cuts both design and verification times.

There will need to be aggressive changes in the way SoC designs are driven within the industry, together with partnerships between companies to drive forward standards for IP inter-operability. The Spirit (Structure for Packaging, Integrating and Re-using IP within Tool-flows) consortium, a group of leading companies in the IP supply chain that includes EDA tool vendors, IP providers and integrated device manufacturers, is one example of current collaboration in this area.

However, any such standards will only gain widespread acceptance if they are effectively deployed within companies and their ability to accelerate the chip design process is proven. One of the essential enablers for this is a mechanism that makes properly configured re-usable IP available to chip designers in a way that allows them to easily select it, understand it and import it into their SoC design environment. The more comprehensive the selection, the more powerful and effective the IP library is.

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