I/O planning ensures IC packaging success

Egino Sarto, CTO, Rio Design Automation
01/30/2006 9:00 AM EST, EE Times

Just as floorplanning has become vital to the success of system-on-chip (SoC) design, package-aware I/O planning is essential for meeting cost, time-to-market and performance targets. Without such planning, excessive package complexity can significantly increase product cost — often pushing a chip’s package cost higher than the cost of its silicon.

Additionally, I/O problems may limit performance and go undetected until verification, and the numerous design cycles required to correct the problems may delay time to market by weeks. Even without such problems, the traditional I/O design methodology adds weeks to SoC design schedules.

Package-aware I/O planning can prevent these problems, especially for critical flip-chip implementations. The main capabilities needed for package-aware I/O planning are I/O synthesis, placement, and routing. I/O synthesis creates an optimized I/O plan combined with cost-effective packaging options, while satisfying physical and electrical constraints.

The most important I/O planning concept is that I/O planning must be part of the overall system design flow, so silicon design teams must deal with package-related issues. Silicon designers need not become packaging experts; packaging guidance can be built into design tools. However, silicon designers do need to understand some packaging concepts that have long been ignored. This white paper explains those concepts and describes package-aware design methodologies that can help meet today’s product goals.

This white paper is therefore an I/O planning overview for silicon design teams. By introducing automated I/O planning early in the design cycle, SoC project managers can ensure good I/O performance for signal integrity, power integrity, physical implementation and lowest overall cost.

More specifically, package-aware I/O planning enables capabilities such as the following for silicon designers:

Optimizing I/O placement to reduce die size and/or fully utilize the die area.
Enabling use of the least expensive package technology while ensuring that performance targets are met.
Getting accurate estimates of load conditions to determine driver strength requirements.
Managing chip/package connectivity within the design environment rather than externally in a spreadsheet.

Design groups can quickly get realistic estimates of packaged chip costs for responding to RFQs.

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