SystemVerilog reference verification methodology: Introduction

Thomas Anderson, Janick Bergeron, Eduard Cerny and Alan Hunter
(03/27/2006 9:00 AM EST), EE Times

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size and complexity of designs. The only way to address this problem is to adopt a reuse-oriented, coverage-driven verification methodology built on the rich semantic support of a standard language.

This is the first in a series of four articles outlining just such a solution: a reference verification methodology enabled by the SystemVerilog hardware design and verification language standard. This methodology is documented in a comprehensive book — the Verification Methodology Manual (VMM) for SystemVerilog — jointly authored by ARM and Synopsys.

The VMM for SystemVerilog addresses how to build a scalable, predictable and reusable environment enabling users to take full advantage of assertions, reusability, testbench automation, coverage, formal analysis, and other advanced technologies to help solve their RTL and system-level verification problems. Such an environment increases user verification confidence for first-pass silicon success. The VMM for SystemVerilog enables all SoC and IP projects to establish an effective, efficient and predictable verification process that is based upon the experience of leading industry experts from ARM, Synopsys, and their customers.

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