SystemVerilog reference verification methodology: RTL

Thomas Anderson, Janick Bergeron, Ed Cerny, Alan Hunter and Andrew Nightingale
(05/01/2006 9:00 AM EDT)

Verification remains the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. As designs continue to grow in size and complexity, new techniques emerge that must be linked by an effective methodology for significant adoption and deployment. The SoC industry needs a reuse-oriented, coverage-driven verification methodology built on the rich semantic support of a standard language.

This is the second in a series of four articles outlining a reference verification methodology enabled by the SystemVerilog hardware design and verification language standard. This methodology is documented in a comprehensive book ï¿½ the Verification Methodology Manual (VMM) for SystemVerilog ï¿½ jointly authored by ARM and Synopsys. This article summarizes some of the key recommendations of the VMM for SystemVerilog for building a scalable, predictable, and reusable environment enabling users to take full advantage of assertions, reusability, testbench automation, coverage, formal analysis, and other advanced verification technologies.

The purpose of the VMM for SystemVerilog is twofold. First, it is intended to educate users about the best practices shown to be effective in assembling a repeatable, productive and robust verification methodology. This allows users to take advantage of the same language capabilities, tool capabilities, and methodology used by verification experts. Second, it enables verification tool vendors to deliver the documentation, SystemVerilog code examples and boilerplates to enable users to take advantage of this methodology quickly and conveniently with a minimum of custom code development.

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