By Andres Takach, Chief Scientist, Mentor Graphics
Jun 2 2006 (0:33 AM), Courtesy of Video/Imaging DesignLine
The algorithms used in video applications are increasingly more sophisticated. The continuous evolution of standards and the highly competitive nature of the industry are challenging design teams to find more efficient flows for implementing video hardware. Traditional design flows require developing the micro architecture, coding the RTL, and verifying the generated RTL against the original functional C or MATLAB specification.
This article presents an overview of a C-based design flow that enables designers to generate high-quality hardware for video algorithms. Algorithmic C synthesis is used to generate optimized RTL from algorithmic specification written in pure ANSI C++. A wide range of micro-architectures for ASIC and FPGA target technologies can be generated from the same source by interactively setting directives during synthesis. The synthesis flow also generates the necessary wrappers so that the original C++ testbench may be used to verify the generated RTL.
A video line filter example is used to illustrate techniques that are useful for coding video algorithms to produce high-performance hardware using C-based design.
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