Core-assisted approach accelerates debug of FPGA DDR II interfaces

In this "How To" tutorial, a debug methodology is described and applied to a real FPGA-based DDR II high-speed memory controller debug example.

By Brad Frieden, Agilent Technologies

With IO rates of several hundred megahertz, FPGAs have become an excellent medium for implementation of high-speed memory controllers. Fast memory storage and retrieval often involve implementing DDR or DDR II memory architectures. Using traditional debug methods, it would be difficult to rapidly debug and validate FPGA systems that interface to DDR memories. However, the evolution of core-assisted debug makes the task dramatically more efficient. In this article, a debug methodology is described and applied to a real DDR II debug example where the design was implemented with Xilinx Virtex 4 FPGAs.

The target system

Let's look at a 200 MHz data rate DDR II memory subsystem, where the designer only had 10 pins available for debug, yet he wanted to look at many signals in the design. Normally, it can be a time-consuming process to manually route signals out to those 10 pins, and then change the design each time new signals are desired. But things are much easier with a core-assisted approach.

The Digital system under test performed data acquisition and processing. Digital data from the outside world was placed into DDR II memory, and then read back from memory upon demand for processing. System prototyping was accomplished using a Xilinx development board that contained Virtex 4 FPGAs. A DDR II memory controller was implemented in a Virtex 4 FPGA and interfaced to external memory control and data paths as shown in Fig 1.

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