A signal conditioner for high-speed serial links

By Lee Wong, Rambus
Jul 5 2006 (9:00 AM), Embedded.com

The incessant demand for faster high speed serial link interconnects has given rise to a plethora of serial link technologies, many of which promise to increase the speed to 12.5Gbps. To achieve the lowest bit error rate margin for a particular channel environment requires careful consideration of a number of critical issues.

This article will discuss the different issues associated with legacy and next-generation backplanes. For instance, manufacturing variations and environmental conditions have a significant impact on the performance of high-speed backplane systems.

System designers must consider these variations and ensure that the systems perform with acceptable bit-error rates under the specified conditions.

The criteria upon which the selection of an appropriate signaling scheme should be made are discussed. In addition, cutting edge serial link technologies, collectively known as Advanced Backplane (ABP), will be discussed. Among the technologies encompassed in ABP are Smart Decision Feedback Equalizer (SmartDFE) and Automatic Adaptation.

Predictions of continued economic recovery and expansion of various data networks drive a resurgence of new design activity at networking equipment vendors.

The result is bandwidth increase that demands dramatic improvements in serial link performance. Developing capable high-performance serial link solutions that comprehensively satisfy the stringent backplane requirements for these platforms poses substantial challenges.

System designers must overcome a host of manufacturing variations, temperature and humidity variations, all of which have significant impact on the performance of high-speed backplane systems. System designers must consider these variations and ensure that the systems perform with acceptable bit-error rates (BERs) under the specified conditions.

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