FPGA Architectures from 'A' to 'Z' : Part 1

If you are new to FPGAs, there are a bewildering number of different architectures and related concepts; but fear not, because this tutorial explains all.

By Clive Maxfield, pldesignline.com
August 15, 2006

Editor's Note: This article is abstracted from Chapter 4 of my book The Design Warrior's Guide to FPGAs, ISBN: 0750676043, with the kind permission of the publisher. I should point out that this book doesn't actually teach you how to design with FPGAs; instead, it provides an introduction to the various device architectures, tools, and design flows (check out the Contents List for more details).

In this article we introduce a plethora of architectural features. Certain options – such as using antifuse versus SRAM configuration cells – are mutually exclusive. Some FPGA vendors specialize in one or the other, while others may offer multiple device families bases on these different technologies. (Unless otherwise noted, the majority of these discussions assume SRAM-based devices.)

In the case of embedded blocks such as multipliers, adders, memory, and microprocessor cores, different vendors offer alternative "flavors" of these blocks with different "recipes" of ingredients. (Much like different brands of chocolate chip cookies featuring larger/smaller chocolate chips, for example, some FPGA families will have bigger/better/badder embedded RAM blocks, while others might feature more multipliers, or support more I/O standards, or . . . the list goes on).

The problem is that the features supported by each vendor and each family change on an almost daily basis. This means that once you've decided what features you need, you then need to do a little research to see which vendor's offerings currently come closest to satisfying your requirements.

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