A tutorial on incremental design using FPGAs from Actel

An "incremental" design flow is highly desirable with regard to repairing or optimizing parts of the design without disturbing portions that have met their design requirements.

By Fred Wickersham, Actel
August 23, 2006 - pldesignline.com

Regardless of the amount of time and energy FPGA designers invest attempting to create "right-first-time" designs, the functional complexities, performance requirements, and high gate counts of large complex designs frequently require changes to correct logic problems or to provide further optimization. Compared with a traditional flow, an "incremental" design flow for design/synthesis and place-and-route physical implementation is highly desirable with regard to repairing or optimizing specific parts of the design without disturbing other portions that have met their design requirements.

When a top-down design approach is difficult due to system memory limitations or extensive run times, an incremental design flow also enables designers to process large designs. Other design strategies involve freezing sections of a completed design while other parts of the design are continuing development independently.

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