SystemVerilog Reference Verification Methodology: VMM Adoption

Thomas Anderson, Janick Bergeron and Eduard Cerny (Synopsys, Inc.) Alan Hunter and Andrew Nightingale (ARM Ltd.)
(09/04/2006 8:22 AM EDT), EE Times

The larger and more complex that system-on-chip (SoC) designs grow, the more verification dominates the development process. In fact, effective design reuse puts even more pressure on the verification team to reduce their part of the schedule. The best solution to this dilemma is the adoption and deployment of a reuse-oriented, coverage-driven methodology that yields more efficient verification, while also increasing the likelihood of first-silicon success.

This is the last in a series of four articles outlining a reference verification methodology that meets these goals for both RTL and system-level verification. This methodology is enabled by the SystemVerilog hardware design and verification language standard and is documented in the Verification Methodology Manual (VMM) for SystemVerilog, a book jointly authored by ARM and Synopsys. This article focuses on ways to adopt the VMM methodology and deploy it quickly throughout an entire SoC project.

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