How to reduce power using I/O gating (CPLDs) versus sleep modes (FPGAs)

By Roger Seaman, Xilinx
September 20, 2006 -- pldesignline.com

Understanding the differences between low power CPLDs (that use built-in I/O gating features to save power) and non-volatile FPGAs (that employ "Sleep Modes").

This article discusses the differences between low power CPLDs with a built-in I/O gating feature, and the various "sleep modes" used by non-volatile FPGAs. Low power CPLDs with I/O gating have many advantages over sleep modes, including the ability to use selected portions of the device. These CPLDs are built on an inherently ultra-low-power patented technology that reduces standby current to as low as 20 microamps.

The technology, known as Fast Zero Power, enables you to build fast, low power handheld consumer devices using programmable logic. Internal input/output (I/O) gating is an advanced feature of these devices that enables the design to gate out unwanted signals during actual operation, thus saving additional power from unwanted toggling of I/Os and downstream logic. You have to ability to select the inputs and outputs for gating, and turn them on and off at will.

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