Analyze DSP algorithms in FPGAs fast with z-transform

By Luc Langlois, Avnet
September 18, 2006, networksystemsdesignline.com

Crafting DSP algorithms for optimum performance in hardware often requires sophisticated design techniques, such as pipelining and overclocked control logic. Such is the case for implementations using the Xilinx Virtex-4 DSP48 slice, which attains maximum efficiency when operating at its peak clock rate of 500 MHz with internal registers enabled.

However, synchronizing calculations in a structure of overclocked pipeline registers can be daunting when using traditional time-domain analysis of waveforms to visualize dataflow. The z-transform is a viable alternative. In this article, I'll present a simple, efficient methodology for analyzing high-performance DSP algorithms using the z-transform to obtain predictable results without guesswork. My examples will demonstrate quick pencil-and-paper calculation techniques of key performance metrics (such as latency) using three different structures of finite impulse response (FIR) filters, with an emphasis on Virtex-4 DSP48-based implementations.

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