How to use CPLDs to manage average power consumption in portable applications

By Roger Seaman, Xilinx    
September 26, 2006

Many designs are challenged by the battery resources of an application. Batteries are limited charge reservoirs with varying capabilities on voltage regulation. Each battery has its own qualities for delivering charge. Many batteries can deliver high currents for brief time periods, or smaller currents for longer times. Trade-offs can and must be made.

Low power CPLDs have additional advanced power saving features to minimize your design's power requirements. In addition to power saving features, such as internal I/O gating, CPLDs can be used to control the power consumption of other devices on your PC board. By analyzing the power profile of your application, you can modify your design to use the CPLD as a power controller. There are three methods for reducing an application's power consumption using low power CPLDs.

• Use an ultra low power CPLD for as many system functions as possible. The CPLDs have up to 12,000 system gates, and the larger devices (256 Macrocell and above) are capable of containing a microcontroller.
• Use the CPLD as a power sequencer for other devices in the design.
• Use the CPLD to gate other devices in the design.

The latter two techniques are discussed in this article. For a discussion of the first technique, see Application Note XAPP387 (PicoBlaze 8-Bit Microcontroller for CPLD Devices) . For a good example of using CPLD for absorbing system functions, see Application Note XAPP390 (Design of a Digital Camera with CoolRunner-II CPLDs) .

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