How to tackle serial backplane challenges with high-performance FPGA designs

Flexible FPGA fabric, embedded multi-gigabit transceivers, and off-the-shelf IP enable robust, high performance, and high-integration serial backplane interface solutions.

By Delfin Rodillas, Xilinx
October 23, 2006 -- pldesignline.com

Serial backplane trends and design challenges

Growing adoption of serial backplanes

The rate of adoption of serial technology in high-end system design has reached critical mass. As shown in Fig 1, this point is supported by the fact that 92% of respondents in a recent EE Times survey answered "yes" when asked if they were designing serial IO systems in 2006. This contrasts to the 64% of positive responses for serial design activity in 2005.

A good portion of this dramatic rate of adoption is due to the penetration of serial technology in backplane applications. As system throughput requirements increase, parallel backplane technologies of old, such as PCI, continue to be displaced by the newer SerDes-based backplane subsystems which provide higher bandwidth, better signal integrity, lower EMI and lower power, as well as simpler PCB designs.

1. Percentage of engineers designing serial IO systems
(CMP EE Times Survey, April, 2005)

Further promoting this growth is the emergence of standard serial protocols such as XAUI, Gigabit Ethernet, and Serial RapidIO which help to reduce engineering efforts and guarantee interoperability. Standardization efforts for serial backplane form factors, such as AdvancedTCA and MicroTCA in the PCI Industrial Computer Manufacturers Group (PICMG), have also contributed to the accelerated adoption. So compelling are the benefits of serial backplanes that they have been used as the backbone of not only communications, compute, and storage systems, but also broadcast, medical, military, and industrial/test systems.

Persistence of design challenges
Regardless of the increased rate of adoption, many design challenges still continue. As the backplane sub-system is the heart of the system, it must be able to pass signals from card to card reliably. Hence designing backplanes with high signal integrity (SI) is of primary importance. Also of significance is the use of proper silicon ICs with SerDes technology that is capable of driving backplanes with very low bit-error rates. Silicon-based approaches to mitigating SI issues becomes particularly important in "legacy upgrade" scenarios where older backplanes with legacy components and design rules are reused.

There are also challenges with regard to developing the serial backplane protocols and complete fabric interface ICs. The majority of backplane designs leverage legacy ASICs with proprietary protocols. Even some newer backplane designs require development of a new proprietary backplane protocol. Therefore, silicon solutions must be flexible and provide the much-needed customizability. While the creation of an ASIC allows this, it can often times be costly and risky with unproven product demand/volume and the possibility of design bugs and specification changes.

An approach that has recently gained traction is the use of off-the-shelf, standards-based switch fabrics. This saves designers development time, but they must have silicon solutions that both conform to the standard protocol and provide the flexibility to customize the end product and differentiate from competitors' products. And of course, there are the ever present challenges of cost, power and time-to-market.

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