|
|
|
|
|
|
 |
||||||||
|
Top 10 methods for ASIC power minimization -- Part 2
By Andreas Olofsson, Analog Devices
January 10, 2007 -- powermanagementdesignline.com This last part describes five effective implementation-level low-power techniques for ASIC power minimization. This is the second part of a two part article focusing on power minimization in deep submicron ASICs. Part 1 illustrates five architectural methods of low power design. The focus of this part is on five effective implementation level low power techniques.
|
|
||||||
|
|
|
|
|
Home | Feedback | Register | Site Map |
|
|
|
All material on this site Copyright © 2017 Design And Reuse S.A. All rights reserved. |
