Using sub-RISC processors in next generation customizable multi-core designs: Part 1

By Andrew Mihal, Scott Weber, and Kurt Keutzer, University of California, Berkeley
Mar 28 2007 (23:15 PM), Embedded.com

The now-common phrase "the processor is the NAND gate of the future" begs the questions: "What kind of processor?" and "How to program them?" When this is discussed, the focus is usually placed on RISC-based processors augmented with instruction extensions as the natural building block. The presumption is that programming will be done in the C language.

Challenging this viewpoint, our opinion is than even a RISC processor is too coarse-grained for typical embedded applications, and that C is insufficient for programming a multiprocessor architecture. As an alternative, we explore the design and deployment of tiny sub-RISC processors as the "NAND gate of the future."

With Tiny Instruction-set Processors and Interconnect (TIPI) processing elements, we can achieve better performance than RISC elements with fewer resource requirements. Also, we can deploy concurrent applications with a programming methodology more productive than C.

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