Embedded-system validation spans inception to signoff

Jim Kenney, Mentor Graphics
(05/21/2007 9:00 AM EDT) -- EE Times

The successful development of embedded systems requires the continuous integration of hardware and firmware throughout all stages of the project. Transaction-level simulation aids in architecture development and refinement, but lacks the detail necessary to confirm that the memory subsystem can support the reset and boot-up process.

Firmware must be executed against a register-transfer-level hardware description, to verify successful boot-up, and against a properly configured real-time operating system hardware-adaptation layer. All intellectual-property (IP) blocks with direct connection to the bus should be verified by processor-driven tests executed on a cycle-accurate CPU. Prior to tapeout, a signoff-accurate processor model must be used to exchange pin-level, timing-accurate bus transactions with all bus masters and slaves. Verifying these processor-driven tests in a virtual environment will ease bring-up when the same tests are run on first silicon.

Across all of these phases of verification, software maintains a singular abstraction level while the hardware description spans transaction level to gates and to physical implementation. Ideally, the tools that span this continuum should present a consistent graphical user interface (GUI) and debug environ- ment for both hardware and firmware execution. There are benefits and trade-offs to hardware/firmware co-development at each level of abstraction, but satisfying certain requirements will yield a homogeneous simulation and debug environment.

Leveraging the embedded core as a tool to inject bus cycles that read and write to IP registers is an attractive adjunct to HDL-based testbenches. As an orthogonal approach to functional verification, processor-driven tests can expose bus interface and timing errors that HDL testbenches may miss. These tests are easy to write, highly portable, work well at all levels of abstraction and can be run on live silicon. As a supplement to manually developed tests, verification teams can adopt big chunks of code from the firmware team. Boot code, hardware diagnostics and the RTOS hardware adaptation layer or board support package are highly relevant to functional verification of the hardware design.

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