Design Constraint Verification and Validation: A New Paradigm

By Jason Ware, Cadence Design Systems, Inc.
June 18, 2007 -- edadesignline.com

Over the years, Electronic Design Automation (EDA) tools have matured considerably. They now aid in design and verification of all aspects of chip manufacturing. One area that has lagged behind is the validation of design constraints. While chip design, functional verification, timing verification and manufacturing have become highly automated, the writing and verification of design constraints has been largely a tedious, manual process.

Today, we have software that can manage, verify and even create design constraints. This allows designers to reduce design cycle times and improve the quality of the design constraints. Improved constraints mean higher quality silicon, especially at finer geometries like 90nm and below (Figure 1).



1. Today's Constraint Management tools can validate and generate constraints for all stages of the design flow.

An extension of constraint validation is exception generation. A constraint management tool can examine the netlist and find functional false paths. The tool must validate these with a proven formal engine to prove the paths can be declared false. Once the paths are proven as false, they can be removed from the cost-equation and static timing analysis of the synthesis and implementation tools. This frees the optimization engine to concentrate on real paths. The benefit is a smaller, faster, cooler design.

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