Analog behavioral models reduce mixed-signal LSI verification time

By Takao Ito, Chief Specialist, Toshiba Corporation
Jun 22, 2007 (12:52 PM) -- Planet Analog

Smaller process geometries are making it possible to take analog components off the board and incorporate them into the chip together with the digital portions of the designs, increasing the complexity of circuits. Even though there is a rapid increase in today's processor performance, simulation for full-chip verification is still taking a long time (Figure 1a and Figure 1b).

Figure 1a: CPU performance and simulation verification trend; taller (blue) bars are CPU performance, lower (yellow) bars are verification times

Figure 1b: Verification time trend

Current methodologies are no longer sufficient or acceptable, so new verification methods are needed.

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