Software-Intensive ASICs/ASSPs Demand Integrated Prototyping Solutions

By Andrew Haines, Synplicity
Jun 22 2007 (8:59 AM), Courtesy of EDA DesignLine

FPGAs continue to march to the tune of Moore's Law with new devices appearing at approximately 2-year intervals. Today, 65 nm FPGAs are available with capacities equivalent to 2M ASIC gates. At these high capacities, and correspondingly high IO counts, 65 nm FPGAs are effective ASIC prototyping vehicles. Based on interaction with customers and our own surveys of ASIC designers, we estimate that over 90 percent of SoCs and ASICs are being prototyped with FPGAs, and the demand for off-the-shelf ASIC prototyping solutions is growing at double-digit rates. So, what's driving the enthusiasm for ASIC prototyping?

The ever-increasing costs of leading-edge ASICs and SoCs are driving semiconductor vendors to seek higher returns on their investment by finding ways for each device to serve broader markets. The increased use of software within these devices provides an effective mechanism to do so. Indeed, increased software content equates to more features, and software variations offer market-specific product differentiation. As a result of this trend to increase software content, it's not uncommon to find a million lines of software code in an ASIC or SoC. Furthermore, the growing use of multi-cores, as forecast by market research firm Gary Smith EDA, will compound the already tremendous growth in software content. This rapid growth of on-chip software is generating new SoC design verification challenges and FPGA-based ASIC prototyping is providing the solutions.

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