Power-Sensitive 65nm Designs Increase the Need for Transistor-Level Verification

By Mike Demler, Synopsys, Inc.
August 27, 2007 -- edadesignline.com

The vision expressed in Moore's Law; that the number of transistors on a chip would double approximately every two years, has been driving the semiconductor industry for many process generations. Most of us have probably committed that statement to memory, and repeated it many times, without ever realizing that it was originally published by Gordon Moore more than forty years ago - in 1965. After four decades we have the capability for fabricating billions of transistors on a chip, but along with that capability comes a new set of challenges to engineers who must verify that a design will meet its objectives before committing to an expensive mask set and processing run.

First and foremost - how can a team of engineers verify the correct functional operation of every one of those billions of transistors in the presence of increasing pressure for shorter time to market? To further add to the challenge, another law has come into effect as well; the law of unintended consequences. As Moore's Law provided for exponential growth in transistors per chip, increasing power density followed as a direct result from doubling the number of devices switching at constantly higher frequencies. This situation becomes more critical when one considers that the largest market driver in the semiconductor industry is now consumer electronics, and the #1 application is cellular handsets that rely on battery operation. Design and process innovations have kept semiconductor technology advancing from one process node to the next, but now the dual challenge of completing functional verification along with verification of complex on-chip power management presents a major obstacle to further progress.

According to the 2006 International Technology Roadmap for Semiconductors Update on Design; many companies are addressing these issues by increasing the number of verification engineers to the point that they now exceed the number of design engineers by two to three times on many projects. The situation may be worse however, because surveys such as this may actually undercount the verification effort by focusing primarily on digital verification engineers, whose role in practicing formal methodologies such as VMM for SystemVerilog is well established and easily identified. Verification tasks performed by designers of analog, memory and custom circuits are not so easily measured.

The 2006 ITRS report also pointed out the growing need for verification of "non-digital effects". It is well known by now that analog/mixed-signal (AMS) content on SoCs has necessarily increased to provide the functionality required in consumer electronics. This in turn has created an increasing demand for AMS verification tools. Not so obvious is the fact that accurate analysis and verification of new generations of power-sensitive designs now requires the use of "non-digital" views of logic blocks and constantly increasing amounts of on-chip memory that can only be provided by AMS solutions. The migration of IC design to the 65nm and 45nm process nodes has increased the need for comprehensive transistor-level verification before tape-out. Verification engineers need not be concerned that their only answer to this problem is more SPICE simulation, which lacks the speed and capacity required for large 65nm circuits, since new solutions are available that deliver increased productivity and accurate, predictable results.

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