Ultra-low-power DSP design

By Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, and Jef Van Meerbergen
August 30, 2007 -- dspdesignline.com

Many emerging applications require extremely low-power DSPs. This article shows how to design such a DSP, using an electrocardiogram application as an example. We show how to achieve low power by tuning the algorithm, processor architecture, and memory system, as well as through clock gating. Throughout the article we present detailed power results to demonstrate the impact of each optimization.

Introduction

A new generation of biomedical monitoring devices is emerging. These applications are typically powered by a tiny battery or an energy scavenger, and have extremely low power budgets. Typical power budgets are around 100 ìW for the whole system, including radio processing, data processing and memories.

To reduce power dissipation of the radio transmitter, system designers often employ feature extraction and/or data compression to reduce the number of bits transmitted. This shifts the power bottleneck from the radio to the data processor, which is the focus of our article. The goal of our work is to create a C-programmable, application-specific DSP optimized for low power. We use a reconfigurable processor from Philips' technology incubator Silicon Hive [4] as starting point.

Click here to read more ...

E-mail This Article

Printer-Friendly Page