FPGA design from scratch

By Sven-Åke Andersson

I have been designing ASICs for more than 15 years. A few years ago I started to realize that there is another player in town and that is the FPGA circuit. With increasing NRE costs and with the long turn-around times, ASIC designs have become high-risk projects. At the same time FPGAs are getting bigger and faster and many companies have therefore decided to only use FPGAs. I also realized that I have to learn how to design using FPGAs, if I were to get any consulting jobs, especially here in Sweden. This is my story of how I hopefully will learn to use FPGAs in my future designs.

Part 1

Introduction
Ordering the MicroBlaze development kit
Installing the Integrated Software Environment (ISE)
Running a board demo test

Design object description

Setting up the Integrated Software Environment (ISE) design software
Running the Integrated Software Environment (ISE) design software

Adding Verilog source code
Generating memories using Coregen
Synthesizing the design
Simulating the design (Introduction)

Setting up the simulation environment using Mongoose

The simulation process
Compiling macro libraries
Compiling the design
Compiling the testbench
Elaborating everything

Testbench description

Using HAL the HDL analysis and linting tool from Cadence

Regression testing using Mongoose

Synthesis using timing constraints (Introduction)

The Field Programmable Gate Array (FPGA) description

Adding synthesis constraints

The MicroBlaze soft processor core
Compiling simulation libraries using compedklib

Putting everything together
Installing ISE WebPack 9.1i
Installing EDK 9.1i

Xilinx Platform Studio XPS
Software Development Kit SDK
Create a new project in XPS
Generate a design report file

Create or import an user peripheral
The MHS file
XPS project files
Xilinx IP center

Adding the ETC IP
Generate the system netlist using platgen
What happend during the netlist generation
Generate simulation HDL files

Putting together a system simulation environment
The simulation database
The cds.lib file
Compiling the ETC IP
Compiling the block RAM
Compiling Verilog wrappers
Compiling VHDL wrappers
Elaborating the design
Warning messages

Generating a Verilog testbench

Running our first simulation
Adding the DDR SDRAM
Suppressing assert messages in IEEE packages

Debugging the simulation testbench
The reset logic

Using the XPS software development kit (SDK)
Software development flow
GNU compiler collection (gcc)
Running SDK
Creating a new C appilcation project

Simulating program execution in the MicroBlaze processor
Verification strategy
Verification flow
Writing a simple c program
Loading the program
Running an NCSIM simulation
Simulation result
Compile and build the program inside SDK
Generate assembly code and hex code
Make a NCSIM memory load file
Running a simulation

System simulations
DDR SDRAM controller
LED displays and push buttons
OPB GPIO registers
Embedded test controller
Debugging the On-Chip Peripheral bus

Implementing the hardware platform
User constraints file
Setting up our constraints file
Specify pin constraints
Specify timing constraints
The implementation directory
Start bitstrem generation
Bitstream generation flow
Scriptfile to run XFlow
Bitstream generation result
Configuration of the FPGA
Using the platform cable USB
ML403 evaluation board
ML403 block diagram
Installing cable drivers
Xilinx JTAG tools on Linux without proprietary kernel modules
Setting up the USB cable
iMPACT FPGA configuration tool
Starting iMPACT

Using the iMPACT configuration tool
Boundary Scan and JTAG configuration
IEE standard 1149.1 (JTAG)
The identification register
Read IDCODE
Read the FPGA status register
Device configuration
Using Xilinx Platform Studio

Pin assignment closure process
PACE Pin and Area Constraint Editor
Running PACE
Topi the Top Code Generator
Topi setup
Using Topi to modify the Xilinx user constraints file
Xilinx Floorplanner
Viewing pin placement
Xilinx PlanAhead

Power calculations
XPower
Low power consumption

Hardware setup
Software setup
Download and execute a simple program
Download the bitstream
Get program size
Running the program

Running demonstration software applications
ML403 Reference Systemson the CD

Adding a 16x2 character LCD display
Set address range
Connecting ports
The easy way to add a new block
Configure the IP block
The LCD driver
LCD display timing
8-bit write operation
Programming sequence
Display setup
More reading
Signal wiring on the ML403 board
Adding constraints
Generate netlist
Generate bitstream

Writing the "Hello World" program
SDK platform settings
C program build
C header files
The GPIO API definitions
C program examples
Device configuartion in SDK

Simulating the LCD driver
C program
Program execution (Waveform plot)
Generating the software libraries and BSPs
GNU compiler tools
Input files
Output files
Output from SDK build process
Display program size

Program disassembly
MicroBlaze software reference guide
System memory layout
Reset sequence
ELF file content
Startup files
First stage initialization files
Second stage initialization files

Generate simualtion HDL files
Simgen
Data2MEM memory tool
ETC_system_sim.bmm
ETC_system_init.vhd
ETC_system_tb.vhd
Modifying the testbench file
Compiling the BRAM initialization file
Compiling the testbench
Simulating program execution

The LCD driver (once more)
Editing the user constraints file
Generate new bitstream
Device configuration
Application program
Displaying "Hello World"

Debugging our design
Xilinx microprocessor debugger and GNU software debugging tools
Xilinx microprocessor debugger (XMD)
MicroBlaze processor target
MicroBlaze MDM hardware setup
Debug session
Reading registers in MicroBlaze
Load program
Set breakpoint
Remove breakpoint
Display breakpoints
Start program execution
Single step
Stop program execution
Display program code
Getting help
Using XMD in Xilinx Platform Studio

Writing software for our embedded system
Writing a software device driver
Software development overview
Device driver programmer guide
Platform specification format reference manual
Microprocessor Driver Definition (MDD)
Libraries and driver generation
Device driver architecture
xparameters.h
Software driver source code
Source code repository
Software device drivers used
SDK project directory
Header source files

Fixing our software driver
etc_v2_1_0.tcl
etc_v2_1_0.mdd
Makefile
xetc_g.c
xetc.h
xetc_l.h
Writing an application program
Print statements
Printout from program
Generate HDL simulation files
Generating the BRAM initialization file
Running a simulation

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